Invention Grant
US08058732B2 Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same
失效
用于晶圆级芯片尺寸封装的半导体晶片结构,用于使用它们的功率器件,封装和系统及其制造方法
- Patent Title: Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same
- Patent Title (中): 用于晶圆级芯片尺寸封装的半导体晶片结构,用于使用它们的功率器件,封装和系统及其制造方法
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Application No.: US12275086Application Date: 2008-11-20
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Publication No.: US08058732B2Publication Date: 2011-11-15
- Inventor: Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
- Applicant: Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
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