Invention Grant
- Patent Title: Logic cell array and bus system
- Patent Title (中): 逻辑单元阵列和总线系统
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Application No.: US12371040Application Date: 2009-02-13
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Publication No.: US08058899B2Publication Date: 2011-11-15
- Inventor: Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
- Applicant: Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
- Agency: Kenyon & Kenyon LLP
- Priority: DE10110530 20010305; DE10111014 20010307; DE10135210 20010724; DE10135211 20010724; DE10139170 20010816; DE10142231 20010829; DE10142894 20010903; DE10142903 20010903; DE10142904 20010903; DE10144732 20010911; DE10144733 20010911; DE10145792 20010917; DE10145795 20010917; DE10146132 20010919
- Main IPC: H03K19/199
- IPC: H03K19/199 ; G06F7/52
Abstract:
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
Public/Granted literature
- US20090146691A1 LOGIC CELL ARRAY AND BUS SYSTEM Public/Granted day:2009-06-11
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