A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element 3, a capacitor element 4 and a connection wiring 6. The connection wiring 6 includes a first polysilicon layer 13a above a substrate 10, and a first silicide layer 14a which connects the resistance element 3 and the capacitor element 4 and is on the first polysilicon layer 13a. The capacitor element 4 includes a diffusion layer 12b in the surface region of the semiconductor substrate 10, a gate insulating layer 15b on the diffusion layer 12b, a second polysilicon layer 13b on the gate insulating layer 15b, and a second silicide layer 14b on the second polysilicon layer 13b. The resistance element 3 includes a third polysilicon layer 13c above the semiconductor substrate 10. The first, second and third polysilicon layers 13a, 13b and 13c are integrally provided. The first and second silicide layers 14a and 14b are integrally provided.