A graphics processing apparatus 2 includes graphics processing pipelines 8. The graphics processing pipelines 8 include a programmable hardware stage 12, a pipeline memory 22 and writeback circuitry 16. Programmable resolving circuitry 18 is provided by the programmable hardware stage 12 within each pipeline and is responsive to one or more graphics program instructions to read pixel values at a first resolution generated within the pipeline memory 22 by pixel value generating circuitry 18 provided by the programmable hardware stage 12 and to perform a resolving operation upon these pixels values so as to generate pixel values at a second resolution. These pixel values at the second resolution are then written back to a frame buffer memory 6.