The flash memory device includes a block switch, first and second cell strings, first and second source lines, drain contacts, and first and second source contacts. The first cell string is connected to a first bit line and a second cell string is connected to a second bit line. The first and second cell strings each include a drain select transistor, a plurality of cell transistors, and a source select transistor connected in series. The drain contacts connect the first and second bit line to a semiconductor substrate. The first and second source contacts connect the first and second source lines to the semiconductor substrate. The first and second source lines in the same block are not adjacent and separated from each other by a predetermined interval.