Invention Grant
- Patent Title: Reducing read failure in a memory device
- Patent Title (中): 减少存储设备中的读取失败
-
Application No.: US12706357Application Date: 2010-02-16
-
Publication No.: US08059474B2Publication Date: 2011-11-15
- Inventor: Seiichi Aritome , Alessandro Torsi , Carlo Musilli
- Applicant: Seiichi Aritome , Alessandro Torsi , Carlo Musilli
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
Public/Granted literature
- US20100142285A1 REDUCING READ FAILURE IN A MEMORY DEVICE Public/Granted day:2010-06-10
Information query