Invention Grant
US08059650B2 Hardware based parallel processing cores with multiple threads and multiple pipeline stages
有权
基于硬件的并行处理核心，具有多个线程和多个流水线阶段
- Patent Title: Hardware based parallel processing cores with multiple threads and multiple pipeline stages
- Patent Title (中): 基于硬件的并行处理核心，具有多个线程和多个流水线阶段
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Application No.: US11932656Application Date: 2007-10-31
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Publication No.: US08059650B2Publication Date: 2011-11-15
- Inventor: Suhas A. Shetty , De B. Vu
- Applicant: Suhas A. Shetty , De B. Vu
- Applicant Address: US CA Sunnyvale
- Assignee: Aruba Networks, Inc.
- Current Assignee: Aruba Networks, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Blakely, Sokoloff, Taylor & Zafman
- Main IPC: H04L12/28
- IPC: H04L12/28
Abstract:
A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.
Public/Granted literature
- US20090109974A1 Hardware Based Parallel Processing Cores with Multiple Threads and Multiple Pipeline Stages Public/Granted day:2009-04-30
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