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US08063657B2 Systems and devices for quantum processor architectures 有权
量子处理器架构的系统和设备

Systems and devices for quantum processor architectures
Abstract:
A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.
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