Invention Grant
- Patent Title: Defect analysis
- Patent Title (中): 缺陷分析
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Application No.: US11824510Application Date: 2007-06-29
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Publication No.: US08064682B2Publication Date: 2011-11-22
- Inventor: Yazan A. Alqudah , Hazem Hajj , Mohamed Abdel Moneum
- Applicant: Yazan A. Alqudah , Hazem Hajj , Mohamed Abdel Moneum
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: G06K9/00
- IPC: G06K9/00

Abstract:
In one embodiment, a method to analyze a semiconductor wafer comprises extracting inline defect data from a data source, counting a total number of inline defects and end-of-line defects, terminating the analysis when the total number of inline defects and end-of-line defects exceeds a threshold, and mapping the inline defects onto the end-of-line defects when the total number of inline defects and end-of-line defects is less than a threshold.
Public/Granted literature
- US20090003684A1 Defect analysis Public/Granted day:2009-01-01
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