Invention Grant
- Patent Title: Scan-based integrated circuit having clock frequency divider
- Patent Title (中): 具有时钟分频器的基于扫描的集成电路
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Application No.: US11937062Application Date: 2007-11-08
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Publication No.: US08065549B2Publication Date: 2011-11-22
- Inventor: Tetsuo Kamada
- Applicant: Tetsuo Kamada
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2006-304448 20061109
- Main IPC: G06F1/12
- IPC: G06F1/12

Abstract:
An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually different frequencies. The synchronous clock circuit unit includes synchronous clock circuits to which the first clock signal, the second clock signal, and the third clock signal are inputted, respectively. The synchronous clock circuits are scanned by use of the first clock signal, the second clock signal, and the third clock signal.
Public/Granted literature
- US20080115005A1 SCAN-BASED INTEGRATED CIRCUIT Public/Granted day:2008-05-15
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