Invention Grant
- Patent Title: Soft error detection logic testing systems and methods
- Patent Title (中): 软错误检测逻辑测试系统和方法
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Application No.: US11760411Application Date: 2007-06-08
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Publication No.: US08065574B1Publication Date: 2011-11-22
- Inventor: Chan-Chi Jason Cheng , Qin Wei , Ting Yew
- Applicant: Chan-Chi Jason Cheng , Qin Wei , Ting Yew
- Applicant Address: US OR Hillsboro
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Hillsboro
- Agency: Haynes and Boone, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G11C29/00 ; G06F11/00

Abstract:
A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.
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