An effective data amount and a power index of a module selected from a design target circuit are extracted from a time-series table database (DB) for each clock cycle. Time periods during which the effective data amount is “0” and there is a high possibility of improving power consumption, are identified. It is determined whether a first simulation result from the design target circuit and a second simulation result from the design target circuit into which a control circuit has been inserted to stop supplying a clock to the module continuously for the identified time periods coincide. Then, if the first simulation result and the second simulation result coincide, the time periods are determined as targets to which a clock gating is applicable.