Invention Grant
US08067819B2 Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line
失效
半导体晶片包括由切割线划分的半导体芯片和在划线上形成的工艺监视电极焊盘
- Patent Title: Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line
- Patent Title (中): 半导体晶片包括由切割线划分的半导体芯片和在划线上形成的工艺监视电极焊盘
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Application No.: US11794649Application Date: 2006-11-22
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Publication No.: US08067819B2Publication Date: 2011-11-29
- Inventor: Masaaki Yoshida , Satoshi Kouno
- Applicant: Masaaki Yoshida , Satoshi Kouno
- Applicant Address: JP Tokyo
- Assignee: Ricoh Company, Ltd.
- Current Assignee: Ricoh Company, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Cooper & Dunham LLP
- Priority: JP2005-339456 20051124; JP2006-006742 20060113
- International Application: PCT/JP2006/023872 WO 20061122
- International Announcement: WO2007/061124 WO 20070531
- Main IPC: H01L23/544
- IPC: H01L23/544
Abstract:
The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer insulation film. The semiconductor wafer includes a process-monitor electrode pad formed on a dicing area of the scribe line. The process-monitor electrode pad has a width greater than the width of the dicing area. The process-monitor electrode pad includes a contact hole formed in the poly-metal insulation film for connecting the first metal wiring layer to the polysilicon layer.
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