An embodiment of the present invention provides an apparatus, comprising a first half cell comprising a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which one or more of the two or more VVCs with the same bias voltage orientation as a signal voltage associated with the apparatus assume one capacitance and one or more of the two or more VVCs with the opposite bias voltage orientation as the signal voltage assume another capacitance, and a second half cell connected in parallel to the first half cell, comprising a circuit with two or more VVCs configured in anti series in which one or more of the two or more VVCs with the same bias voltage orientation as a signal voltage associated with the apparatus assume the same values as the anti-oriented VVCs in the first half cell and a one or more VVCs with the opposite bias voltage orientation as a signal voltage assume the same values as the like oriented VVCs in the first half cell.