Invention Grant
US08067956B2 Apparatus and method for calibrating on-die termination in semiconductor memory device
有权
用于校准半导体存储器件中的管芯端接的装置和方法
- Patent Title: Apparatus and method for calibrating on-die termination in semiconductor memory device
- Patent Title (中): 用于校准半导体存储器件中的管芯端接的装置和方法
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Application No.: US12013804Application Date: 2008-01-14
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Publication No.: US08067956B2Publication Date: 2011-11-29
- Inventor: Dong Uk Lee
- Applicant: Dong Uk Lee
- Applicant Address: KR
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR
- Agency: Baker & McKenzie LLP
- Priority: KR10-2007-0035858 20070412
- Main IPC: H03K17/16
- IPC: H03K17/16
Abstract:
An on-die termination circuit in a semiconductor memory apparatus can comprise a comparing block for comparing a reference voltage with a code voltage corresponding to a code and outputting a comparison signal, a counting block for changing the code based on the comparison signal, and controlling block for controlling the counting block based on a match result of previous and current values of the comparison signal.
Public/Granted literature
- US20080253201A1 APPARATUS AND METHOD FOR CALIBRATING ON-DIE TERMINATION IN SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2008-10-16
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