Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells.