Invention Grant
US08069102B2 Method and apparatus for processing financial information at hardware speeds using FPGA devices
有权
使用FPGA器件以硬件速度处理财务信息的方法和装置
- Patent Title: Method and apparatus for processing financial information at hardware speeds using FPGA devices
- Patent Title (中): 使用FPGA器件以硬件速度处理财务信息的方法和装置
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Application No.: US11561615Application Date: 2006-11-20
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Publication No.: US08069102B2Publication Date: 2011-11-29
- Inventor: Ronald S. Indeck , Ron Kaplan Cytron , Mark Allen Franklin , Roger D. Chamberlain
- Applicant: Ronald S. Indeck , Ron Kaplan Cytron , Mark Allen Franklin , Roger D. Chamberlain
- Applicant Address: US MO St. Louis
- Assignee: Washington University
- Current Assignee: Washington University
- Current Assignee Address: US MO St. Louis
- Agency: Thompson Coburn LLP
- Main IPC: G06Q40/00
- IPC: G06Q40/00
Abstract:
A method and apparatus use decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price.
Public/Granted literature
- US20070078837A1 Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices Public/Granted day:2007-04-05
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