An SE0 timer detects that an SE0 state of a universal serial bus continues for 3 ms or more, and asserts an SE03ms detected signal to a suspending/reset discriminating circuit. The suspending/reset discriminating circuit connects a pull-up resistor to a D+ data line, detects that the universal serial bus is in the SE0 state, and asserts a reset detected signal to a reset control circuit. The reset control circuit asserts a threshold level changing signal to a receiver for a high-speed mode. The receiver changes the threshold into 250 mV. When the reset control circuit detects a K state of the universal serial bus after chirp driving K is executed and ended, the reset control circuit negates the threshold level changing signal to the receiver. The receiver changes the threshold back to 125 mV.