A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (11) and a second flip-flop that samples an output of the second selector. An address and control signal and write data output from the first and second flip-flops are supplied to an address and control terminal and a write data terminal of the memory.