Invention Grant
- Patent Title: Two-step subranging ADC architecture
- Patent Title (中): 两步子程序ADC架构
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Application No.: US12684735Application Date: 2010-01-08
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Publication No.: US08077069B2Publication Date: 2011-12-13
- Inventor: Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
- Applicant: Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H03M1/14
- IPC: H03M1/14

Abstract:
First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.
Public/Granted literature
- US20100182178A1 Two-Step Subranging ADC Architecture Public/Granted day:2010-07-22
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