Invention Grant
- Patent Title: Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials
- Patent Title (中): 铁电存储器,子位线相互连接并固定电位
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Application No.: US12471059Application Date: 2009-05-22
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Publication No.: US08077494B2Publication Date: 2011-12-13
- Inventor: Hideaki Miyamoto
- Applicant: Hideaki Miyamoto
- Applicant Address: US DE Wilmington
- Assignee: Patrenella Capital Ltd., LLC
- Current Assignee: Patrenella Capital Ltd., LLC
- Current Assignee Address: US DE Wilmington
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Priority: JP2006-121425 20060426
- Main IPC: G11C11/22
- IPC: G11C11/22

Abstract:
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
Public/Granted literature
- US20090231904A1 FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS Public/Granted day:2009-09-17
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