Invention Grant
- Patent Title: Small unit internal verify read in a memory device
- Patent Title (中): 小单元内部验证读入存储器件
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Application No.: US12552743Application Date: 2009-09-02
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Publication No.: US08077532B2Publication Date: 2011-12-13
- Inventor: Tetsuji Manabe , Satoru Tamada
- Applicant: Tetsuji Manabe , Satoru Tamada
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable.
Public/Granted literature
- US20110051523A1 SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE Public/Granted day:2011-03-03
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