Invention Grant
- Patent Title: Multiple-word multiplication-accumulation circuit and montgomery modular multiplication-accumulation circuit
- Patent Title (中): 多字乘法积累电路和montgomery模乘法积累电路
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Application No.: US10898178Application Date: 2004-07-26
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Publication No.: US08078661B2Publication Date: 2011-12-13
- Inventor: Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
- Applicant: Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Fujitsu Patent Center
- Priority: JP2004-017205 20040126
- Main IPC: G06F7/38
- IPC: G06F7/38

Abstract:
A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.
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