Invention Grant
US08080468B2 Methods for fabricating passivated silicon nanowires and devices thus obtained
有权
制备钝化硅纳米线的方法和由此获得的器件
- Patent Title: Methods for fabricating passivated silicon nanowires and devices thus obtained
- Patent Title (中): 制备钝化硅纳米线的方法和由此获得的器件
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Application No.: US12822109Application Date: 2010-06-23
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Publication No.: US08080468B2Publication Date: 2011-12-20
- Inventor: Axel Scherer , Sameer Walavalkar , Michael D. Henry , Andrew P. Homyk
- Applicant: Axel Scherer , Sameer Walavalkar , Michael D. Henry , Andrew P. Homyk
- Applicant Address: US CA Pasadena
- Assignee: California Institute of Technology
- Current Assignee: California Institute of Technology
- Current Assignee Address: US CA Pasadena
- Agency: Steinfl & Bruno LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/20 ; H01L21/36
Abstract:
Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.
Public/Granted literature
- US20110031470A1 METHODS FOR FABRICATING PASSIVATED SILICON NANOWIRES AND DEVICES THUS OBTAINED Public/Granted day:2011-02-10
Information query
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