Invention Grant
- Patent Title: Semiconductor integrated circuit and unstable bit detection method for the same
- Patent Title (中): 半导体集成电路和不稳定位检测方法相同
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Application No.: US12314978Application Date: 2008-12-19
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Publication No.: US08081510B2Publication Date: 2011-12-20
- Inventor: Tomonori Hayashi
- Applicant: Tomonori Hayashi
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-337434 20071227
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of pieces of readout data, and an OK/NG determination circuit for comparing the plurality of pieces of readout data to determine whether the nonvolatile memory cell is stable or not.
Public/Granted literature
- US20090168539A1 Semiconductor integrated circuit and unstable bit detection method for the same Public/Granted day:2009-07-02
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