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US08081510B2 Semiconductor integrated circuit and unstable bit detection method for the same 失效
半导体集成电路和不稳定位检测方法相同

Semiconductor integrated circuit and unstable bit detection method for the same
Abstract:
A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of pieces of readout data, and an OK/NG determination circuit for comparing the plurality of pieces of readout data to determine whether the nonvolatile memory cell is stable or not.
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