Invention Grant
- Patent Title: Enhanced microprocessor interconnect with bit shadowing
- Patent Title (中): 增强的微处理器互连与位阴影
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Application No.: US12165848Application Date: 2008-07-01
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Publication No.: US08082475B2Publication Date: 2011-12-20
- Inventor: Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
- Applicant: Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Main IPC: G06F11/14
- IPC: G06F11/14 ; G06F11/30

Abstract:
Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
Public/Granted literature
- US20100005349A1 ENHANCED MICROPROCESSOR INTERCONNECT WITH BIT SHADOWING Public/Granted day:2010-01-07
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