In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.