Invention Grant
US08086916B2 System and method for running test and redundancy analysis in parallel
有权
并行运行测试和冗余分析的系统和方法
- Patent Title: System and method for running test and redundancy analysis in parallel
- Patent Title (中): 并行运行测试和冗余分析的系统和方法
-
Application No.: US12490657Application Date: 2009-06-24
-
Publication No.: US08086916B2Publication Date: 2011-12-27
- Inventor: Kristopher Kopel
- Applicant: Kristopher Kopel
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.
Public/Granted literature
- US20090265588A1 SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL Public/Granted day:2009-10-22
Information query