Invention Grant
US08087024B2 Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache
失效
具有L1指令高速缓存和共享L2指令高速缓存的多个多线程处理器
- Patent Title: Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache
- Patent Title (中): 具有L1指令高速缓存和共享L2指令高速缓存的多个多线程处理器
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Application No.: US12313247Application Date: 2008-11-18
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Publication No.: US08087024B2Publication Date: 2011-12-27
- Inventor: Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
- Applicant: Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F13/00 ; G06F12/00 ; G06F15/76 ; G06F9/44
Abstract:
In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
Public/Granted literature
- US20090089546A1 Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache Public/Granted day:2009-04-02
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