Invention Grant
- Patent Title: Method of fabricating vertical capacitors in through-substrate vias
- Patent Title (中): 在通孔中制造垂直电容器的方法
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Application No.: US12291263Application Date: 2008-11-05
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Publication No.: US08088667B2Publication Date: 2012-01-03
- Inventor: Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou , Robert L. Borwick, III
- Applicant: Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou , Robert L. Borwick, III
- Applicant Address: US CA Thousand Oaks
- Assignee: Teledyne Scientific & Imaging, LLC
- Current Assignee: Teledyne Scientific & Imaging, LLC
- Current Assignee Address: US CA Thousand Oaks
- Agency: Koppel, Patrick, Heybl & Philpott
- Main IPC: H01L21/443
- IPC: H01L21/443

Abstract:
A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.
Public/Granted literature
- US20100110607A1 Vertical capacitors and method of fabricating same Public/Granted day:2010-05-06
Information query
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