Invention Grant
- Patent Title: Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
- Patent Title (中): 用于制造集成电路的方法,该栅极电极电平区域包括至少三个线性导电结构的两个并排电极,其通过非栅极电平彼此电连接
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Application No.: US12572232Application Date: 2009-10-01
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Publication No.: US08088682B2Publication Date: 2012-01-03
- Inventor: Scott T. Becker , Michael C. Smayling
- Applicant: Scott T. Becker , Michael C. Smayling
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205

Abstract:
A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.
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