Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes

Invention Grant

US08089100B2 Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes 有权

Title translation: 具有栅极电平区域的集成电路，包括形成晶体管的栅电极的至少四个线状导电结构，并且包括至少两个不同尺寸的延伸部分

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Patent Title: Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes
Patent Title (中): 具有栅极电平区域的集成电路，包括形成晶体管的栅电极的至少四个线状导电结构，并且包括至少两个不同尺寸的延伸部分
Application No.: US12567528

Application Date: 2009-09-25
Publication No.: US08089100B2

Publication Date: 2012-01-03
Inventor: Scott T. Becker , Michael C. Smayling
Applicant: Scott T. Becker , Michael C. Smayling
Applicant Address: US CA Los Gatos
Assignee: Tela Innovations, Inc.
Current Assignee: Tela Innovations, Inc.
Current Assignee Address: US CA Los Gatos
Agency: Martine Penilla Group, LLP
Main IPC: H01L27/10
IPC: H01L27/10

Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes

Abstract:

A restricted layout region includes a diffusion level layout including diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A total number of PMOS and NMOS transistor devices in the restricted layout region is greater than or equal to eight. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract(Chinese):

限制布局区域包括扩散级布局，其包括限定至少一个p型扩散区域的扩散区域布局形状和由中心非活性区域分隔开的至少一个n型扩散区域。栅电极层布局被限定在衬底部分上方，以包括仅在第一平行方向上延伸的线性布局特征。在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由半导体器件制造能力。限制布局区域中的PMOS和NMOS晶体管器件的总数大于或等于8。限制布局区域对应于单元布局的整个栅电极层。

Public/Granted literature

US20100017766A1 Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors Public/Granted day:2010-01-21

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L27/00	由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件（其零部件入H01L23/00，H01L29/00至H01L51/00；由多个单个固态器件组成的组装件入H01L25/00）
H01L27/02	.包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的；包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的
H01L27/04	..其衬底为半导体的
H01L27/10	...在重复结构中包括有多个独立组件的