Invention Grant
- Patent Title: Semiconductor memory device
- Patent Title (中): 半导体存储器件
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Application No.: US12562781Application Date: 2009-09-18
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Publication No.: US08089120B2Publication Date: 2012-01-03
- Inventor: Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi , Yoshiaki Fukuzumi
- Applicant: Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi , Yoshiaki Fukuzumi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-282817 20081104
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113

Abstract:
A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.
Public/Granted literature
- US20100109071A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2010-05-06
Information query
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