Nonvolatile semiconductor memory device and method of manufacturing the same

Invention Grant

US08089121B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效

Title translation: 非易失性半导体存储器件及其制造方法

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Patent Title: Nonvolatile semiconductor memory device and method of manufacturing the same
Patent Title (中): 非易失性半导体存储器件及其制造方法
Application No.: US12564605

Application Date: 2009-09-22
Publication No.: US08089121B2

Publication Date: 2012-01-03
Inventor: Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Masaru Kito
Applicant: Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Masaru Kito
Applicant Address: JP Tokyo
Assignee: Kabushiki Kaisha Toshiba
Current Assignee: Kabushiki Kaisha Toshiba
Current Assignee Address: JP Tokyo
Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
Priority: JP2008-293150 20081117
Main IPC: H01L21/8246
IPC: H01L21/8246 ; H01L27/115

Nonvolatile semiconductor memory device and method of manufacturing the same

Abstract:

A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.

Abstract(Chinese):

非易失性半导体存储器件包括作为沟道的半导体层，在半导体层的表面上形成有第一绝缘层和介于其间的第二绝缘层的导电层，用作控制栅电极; 以及形成在所述第一绝缘层和所述第二绝缘层之间的多个第一电荷存储层。多个第一电荷存储层沿着第一绝缘层的表面彼此隔离地形成。第一绝缘层形成为在形成有第一电荷存储层的位置处向半导体层突出。

Public/Granted literature

US20100123180A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2010-05-20

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8246	.........只读存储器结构（ROM）