Invention Grant
US08089295B2 Wafer level balanced capacitance design for magnetic heads 有权
晶圆平衡电容设计用于磁头

Wafer level balanced capacitance design for magnetic heads
Abstract:
Embodiments of the invention provide methods, systems and apparatus for testing electronic components, and more specifically for testing magnetoresistive heads. A pair of top shield pads and a pair of bottom shield pads may be formed in a kerf region of a wafer on which magnetoresistive heads are formed. The top shield pads, bottom shield pads, and a magnetoresistive head may form a circuit that may be coupled with a testing circuit to exchange test signals configured to test the magnetic head. The pair of bottom shield pads may provide balanced impedance to substrate that nullifies the effects of broadband noise.
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