Invention Grant
- Patent Title: Wafer level balanced capacitance design for magnetic heads
- Patent Title (中): 晶圆平衡电容设计用于磁头
-
Application No.: US11967478Application Date: 2007-12-31
-
Publication No.: US08089295B2Publication Date: 2012-01-03
- Inventor: Arley Cleveland Marley , David John Seagle
- Applicant: Arley Cleveland Marley , David John Seagle
- Applicant Address: NL Amsterdam
- Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee Address: NL Amsterdam
- Agency: Patterson & Sheridan, LLP
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G11B5/127

Abstract:
Embodiments of the invention provide methods, systems and apparatus for testing electronic components, and more specifically for testing magnetoresistive heads. A pair of top shield pads and a pair of bottom shield pads may be formed in a kerf region of a wafer on which magnetoresistive heads are formed. The top shield pads, bottom shield pads, and a magnetoresistive head may form a circuit that may be coupled with a testing circuit to exchange test signals configured to test the magnetic head. The pair of bottom shield pads may provide balanced impedance to substrate that nullifies the effects of broadband noise.
Public/Granted literature
- US20090168259A1 WAFER LEVEL BALANCED CAPACITANCE DESIGN FOR MAGNETIC HEADS Public/Granted day:2009-07-02
Information query