Invention Grant
- Patent Title: Tiled prefetched and cached depth buffer
- Patent Title (中): 平铺预取和缓存深度缓冲区
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Application No.: US11086474Application Date: 2005-03-21
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Publication No.: US08089486B2Publication Date: 2012-01-03
- Inventor: Michael Hugh Anderson , Dan Minglun Chuang , Geoffrey Shippee , Rajat Rajinderkumar Dhawan , Chun Yu
- Applicant: Michael Hugh Anderson , Dan Minglun Chuang , Geoffrey Shippee , Rajat Rajinderkumar Dhawan , Chun Yu
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Timothy F. Loomis; James R. Gambale
- Main IPC: G06T1/20
- IPC: G06T1/20

Abstract:
A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.
Public/Granted literature
- US20060209078A1 Tiled prefetched and cached depth buffer Public/Granted day:2006-09-21
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