Invention Grant
- Patent Title: Correction arithmetic circuit
- Patent Title (中): 校正算术电路
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Application No.: US12249553Application Date: 2008-10-10
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Publication No.: US08089490B2Publication Date: 2012-01-03
- Inventor: Nobuhiko Omori
- Applicant: Nobuhiko Omori
- Applicant Address: JP Osaka JP Gunma
- Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.
- Current Assignee Address: JP Osaka JP Gunma
- Agency: Osha • Liang LLP
- Priority: JP2007-265570 20071011
- Main IPC: G09G5/02
- IPC: G09G5/02

Abstract:
A plurality of one-port split lookup tables having alternately stored therein correction data corresponding to input data is provided as a lookup table that has stored therein the correction data corresponding to the input data at predetermined intervals relevant to predetermined higher-order bits. An address generating unit generates addresses for a plurality of the corresponding split lookup tables from the input data. An interpolation arithmetic unit executes interpolation arithmetic with the use of lower-order bits of the input data for readout data read from two lookup tables.
Public/Granted literature
- US20090096805A1 CORRECTION ARITHMETIC CIRCUIT Public/Granted day:2009-04-16
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