During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.