A method and a circuit for obtaining asynchronous demapping clock. The method includes: obtaining a smoothed clock with even gaps in accordance with data to be demapped and a corresponding clock signal; performing phase locking in accordance with a signal reflecting writing and reading conditions of data of a First In First Out (FIFO), to obtain a clock signal required for demapping. The method can effectively filter off jittering created during asynchronous mapping/demapping processes and may ensure a high-performance clock output. Furthermore, the method is applicable to not only mapping from OTN to SDH but also other asynchronous demapping processes, e.g., mapping from SDH to OTN, and thereby effectively improving the performance of data demapping.