Invention Grant
US08090068B2 System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL)
有权
用于数字锁相环(DPLL)的时间 - 数字转换器(TDC)校准电源门控窗口的系统和方法
- Patent Title: System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL)
- Patent Title (中): 用于数字锁相环(DPLL)的时间 - 数字转换器(TDC)校准电源门控窗口的系统和方法
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Application No.: US12107584Application Date: 2008-04-22
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Publication No.: US08090068B2Publication Date: 2012-01-03
- Inventor: Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
- Applicant: Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM, Incorporated
- Current Assignee: QUALCOMM, Incorporated
- Current Assignee Address: US CA San Diego
- Agent Larry Moskowitz; William M. Hooks
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
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Information query
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