Invention Grant
US08090967B2 Power state transition initiation control of memory interconnect based on early warning signal, memory response time, and wakeup delay
有权
基于预警信号，存储器响应时间和唤醒延迟的存储器互连的功率状态转换启动控制
- Patent Title: Power state transition initiation control of memory interconnect based on early warning signal, memory response time, and wakeup delay
- Patent Title (中): 基于预警信号，存储器响应时间和唤醒延迟的存储器互连的功率状态转换启动控制
-
Application No.: US12126540Application Date: 2008-05-23
-
Publication No.: US08090967B2Publication Date: 2012-01-03
- Inventor: Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
- Applicant: Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32
Abstract:
A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.
Public/Granted literature
- US20090292935A1 Method, System and Apparatus for Power Management of a Link Interconnect Public/Granted day:2009-11-26
Information query
