Invention Grant
- Patent Title: Disabling portions of memory with defects
- Patent Title (中): 禁用存在缺陷的部分
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Application No.: US12540602Application Date: 2009-08-13
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Publication No.: US08091000B2Publication Date: 2012-01-03
- Inventor: Tsung-Yung (Jonathan) Chang , Durgesh Srivastava , Jonathan Shoemaker , John Benoit
- Applicant: Tsung-Yung (Jonathan) Chang , Durgesh Srivastava , Jonathan Shoemaker , John Benoit
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F12/08

Abstract:
An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.
Public/Granted literature
- US20090300413A1 DISABLING PORTIONS OF MEMORY WITH DEFECTS Public/Granted day:2009-12-03
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