Invention Grant
US08091004B2 Inter-packet selective symbol mapping in a joint incremental redundancy and symbol mapping diversity system
有权
联合增量冗余和符号映射分集系统中的分组间选择性符号映射
- Patent Title: Inter-packet selective symbol mapping in a joint incremental redundancy and symbol mapping diversity system
- Patent Title (中): 联合增量冗余和符号映射分集系统中的分组间选择性符号映射
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Application No.: US12102584Application Date: 2008-04-14
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Publication No.: US08091004B2Publication Date: 2012-01-03
- Inventor: Vladislav A Chernyshev , Andrey Efimov , Mikhail Lyakh
- Applicant: Vladislav A Chernyshev , Andrey Efimov , Mikhail Lyakh
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
An integrated incremental redundancy symbol mapping diversity system for a communication device. The integrated incremental redundancy symbol mapping diversity system includes a transmitter. The transmitter packetizes a retransmission packet according to a modulation scheme in response to a retransmission request from the receiver. The transmitter includes an output packet processor and an inter-packet selective symbol mapper. The output packet processor determines a transmission iteration of a bit segment of the retransmission packet. The inter-packet selective symbol mapper applies a first symbol map pattern to the bit segment based on the transmission iteration of the bit segment and applies a second symbol map pattern to another bit segment of the retransmission packet based on the transmission iteration of the other bit segment. The first symbol map pattern is different from the second symbol map pattern.
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