Invention Grant
- Patent Title: Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof
- Patent Title (中): 集成电路封装系统具有通过直通互连的硅通孔及其制造方法
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Application No.: US12949835Application Date: 2010-11-19
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Publication No.: US08093100B2Publication Date: 2012-01-10
- Inventor: A Leam Choi , Jae Han Chung , DeokKyung Yang , HyungSang Park
- Applicant: A Leam Choi , Jae Han Chung , DeokKyung Yang , HyungSang Park
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agent Mikio Ishimaru
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
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