Invention Grant
US08093146B2 Method of fabricating gate electrode using a hard mask with spacers
有权
使用具有间隔物的硬掩模制造栅电极的方法
- Patent Title: Method of fabricating gate electrode using a hard mask with spacers
- Patent Title (中): 使用具有间隔物的硬掩模制造栅电极的方法
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Application No.: US12725814Application Date: 2010-03-17
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Publication No.: US08093146B2Publication Date: 2012-01-10
- Inventor: Shiang-Bau Wang
- Applicant: Shiang-Bau Wang
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a hard mask layer over the gate material layers; patterning the hard mask layer to from a hard mask pattern; forming a spacer layer over the hard mask pattern; etching back the spacer layer to form spacers over sidewalls of the hard mask pattern; etching the gate material layers by using the spacers and the hard mask pattern as an etching mask to form a gate structure; and performing a tilt-angle ion implantation process to the semiconductor substrate.
Public/Granted literature
- US20110230029A1 METHOD OF FABRICATING GATE ELECTRODE USING A HARD MASK WITH SPACERS Public/Granted day:2011-09-22
Information query
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