Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US12204565Application Date: 2008-09-04
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Publication No.: US08093683B2Publication Date: 2012-01-10
- Inventor: Tetsuo Shimamura
- Applicant: Tetsuo Shimamura
- Applicant Address: JP Gunma US AZ Phoenix
- Assignee: SANYO Semiconductor Co., Ltd.,Semiconductor Components Industries, LLC
- Current Assignee: SANYO Semiconductor Co., Ltd.,Semiconductor Components Industries, LLC
- Current Assignee Address: JP Gunma US AZ Phoenix
- Agency: Morrison & Foerster LLP
- Priority: JP2007-231766 20070906
- Main IPC: H01L29/735
- IPC: H01L29/735

Abstract:
The invention is directed to providing a technique for increasing a hold voltage of an electrostatic breakdown protection device having a bipolar transistor structure more than conventional and reducing the size of the device. A base region (a P impurity layer) is formed on a front surface of an epitaxial layer, an emitter region (an N+ impurity layer) is formed on the front surface of the P impurity layer, and the epitaxial layer and an N+ impurity layer form a collector region. A connected portion of a base electrode and the base region (the P impurity layer) is located between the end of the base region (the P impurity layer) on a collector electrode side and the emitter region (the N+ impurity layer). It means that the electrodes for the collector, the base and the emitter are formed in this order. The base electrode and the emitter electrode are connected through a wiring (not shown). A P+ isolation layer for dividing the epitaxial layer into a plurality of island regions is further formed.
Public/Granted literature
- US20090065899A1 SEMICONDUCTOR DEVICE Public/Granted day:2009-03-12
Information query
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