Invention Grant
- Patent Title: Method of manufacturing a semiconductor integrated circuit device
- Patent Title (中): 制造半导体集成电路器件的方法
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Application No.: US13098648Application Date: 2011-05-02
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Publication No.: US08093723B2Publication Date: 2012-01-10
- Inventor: Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
- Applicant: Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2002-181974 20020621
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
Public/Granted literature
- US20110204486A1 METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2011-08-25
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