It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits (11-1, 11-2, . . . ) that extract a data pattern supplied to a complete operating article chip (10) in a BOST (3) from the BOST and that successively transmit the data pattern in response to a clock signal, and second transfer circuits (12-1, 12-2, . . . ) that extract output data from the complete operating article chip (10) as an expectation value pattern and that successively transmit the expectation value pattern in response to the clock signal. The data pattern supplied to the complete operating article chip (10) is applied to one chip to be measured (10-1) and the data pattern from a corresponding stage of the first transfer circuits (11-1, 11-2, . . . ) is applied to each of other chips to be measured (10-2, . . . ). A comparator (14-1) compares output data from the one chip to be measured (10-1) to the output data from the complete operating article chip (10) to decide whether or not they coincide. Corresponding to the other chips to be measured (10-2, . . . ), a comparator (14-2, . . . ) compares respective output data from the other chips to be measured to the expectation value pattern from the corresponding stage of the second transfer circuits (12-1, 12-2, . . . ) to decide whether or not they coincide.