A system and method to perform automatic testing of a device using Design-for-Test functionality built-in a pair of serializer/deserializer (SERDES) of the device to perform I/O characterization with respect to clock jitter in a self-test mode. Performance of a SERDES operating with jitter injected clock signal is characterized by forming a self-test loop-back configuration with another SERDES operating with a clean clock signal where the clean clock signal and the jitter injected clock signal are supplied by a simplified tester.