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US08097517B2 Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS 失效
具有改善的PMOS的短沟道效应和NMOS的稳定电流的半导体器件的制造方法

  • Patent Title: Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS
  • Patent Title (中): 具有改善的PMOS的短沟道效应和NMOS的稳定电流的半导体器件的制造方法
  • Application No.: US12791131
    Application Date: 2010-06-01
  • Publication No.: US08097517B2
    Publication Date: 2012-01-17
  • Inventor: Min Jung Shin
  • Applicant: Min Jung Shin
  • Applicant Address: KR Kyoungki-do
  • Assignee: Hynix Semiconductor Inc.
  • Current Assignee: Hynix Semiconductor Inc.
  • Current Assignee Address: KR Kyoungki-do
  • Agency: Ladas & Parry LLP
  • Priority: KR10-2007-0116055 20071114
  • Main IPC: H01L21/8238
  • IPC: H01L21/8238
Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS
Abstract:
The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.
Abstract(Chinese):

本发明涉及能够同时改善PMOS的短沟道效应和NMOS的电流的半导体器件及其制造方法。 半导体器件分别包括在半导体衬底的第一和第二区域上形成的第一和第二栅极; 以及形成在半导体衬底的对应于第一栅极的两侧的部分中的第一和第二接合区域以及与第二栅极的两侧相对应的半导体衬底的一部分，并且包括突起， 第一接合区域的高度高于第二接合区域的突起的高度，并且第二接合区域形成为使得其具有比第一接合区域的深度更深的半导体衬底的表面的深度。

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IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70 .由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77 ..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78 ...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82 ....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822 .....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232 ......场效应工艺
H01L21/8234 .......MIS工艺
H01L21/8238 ........互补场效应晶体管，例如CMOS
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